In some computing systems, a data bus such as an input/output data bus for a memory device may be arranged to operate with double data rate (DDR) transfers of data on both rising and falling edges of a clock signal. DDR may be utilized to achieve higher data transmission rates for accessing various types of volatile or non-volatile memory. A precision of a clock duty cycle is important due to both the rising and falling edges of the clock signal being utilized to enable the higher data transmission rates.